In general, information processing devices including image processing devices use a Dynamic Random Access Memory (DRAM) with a large capacity and a low cost in order to store a huge amount of data. Especially, recent image processing devices are required, for example, to correspond to High Definition (HD) image processing according to standards such as MPEG-2 and H.264, to deal with a plurality of channels at once, and to process high-resolution 3-dimensional graphics. Therefore, the devices need a DRAM having high-level data transfer performance (hereinafter, referred to as a “memory band”) as well as a large capacity.
Well known methods for achieving a high memory band are a method (1) by increasing a bus operating frequency, a method (2) by increasing of a bus width of a memory, and a method by combining (1) with (2).
In general, in order to access a DRAM, activation processing is to be performed by previously designating a bank and a row to be accessed. If a row to be accessed is to be changed to another in the same bank, pre-charge processing is performed on an accessed row and activation processing is performed on a next row to be accessed. During the activation processing and the pre-charge processing, it is impossible to access the bank. Therefore, switching of rows in the same bank produces a time period during which access is impossible (hereinafter, referred to as an “inaccessible period”). As a result, there is a drawback of producing an idle time of a data bus.
In order to overcome the drawback, so-called bank interleave control is performed when accesses to a DRAM are controlled. In the bank interleave control, while data is transferred to a certain bank, activation processing and pre-charge processing are performed for a different bank. Thereby, an inaccessible period is concealed, and data can be virtually transferred any time on a data bus. The bank interleave control can efficiently work, when an inaccessible period for a certain bank is shorter than a data transfer period for a different bank.
Whichever of the above methods (1) and (2) is adopted to achieve a high memory band, an absolute period of the inaccessible period is never changed while a data transfer amount for each unit time is increased. Therefore, a data transfer amount required to conceal an inaccessible period is also increased. This means that a data transfer amount required to conceal an inaccessible period is increased.
As a result, the bank interleave control cannot adequately conceal an inaccessible period, unless a data transfer amount for other banks is increased, in other words, unless a transfer size for each access is increased. Thereby, a data bus has an idle time, causing a problem of reducing access efficiency. This significantly reduces access efficiency in a system having frequent accesses with a small transfer size.
One of conventional techniques of addressing the above problem is disclosed in Patent Reference 1. In the technique of Patent Reference 1, a plurality of memory devices in a single logical address space are accessed via respective different address buses. This structure improves access efficiency in terms of a total data bus width of the memory devices.
In the technique of Patent Reference 1, an address bus is independently controlled for each memory device. Therefore, a minimum access unit is reduced more than that in the situation where a single address bus is shared among a plurality of memory devices. The technique of Patent Reference 1 can thereby eliminate unnecessary data for the total data bus width of the memory devices. As a result, the technique of Patent Reference 1 can suppress reducing access efficiency in a system having frequent accesses with a small transfer size.    Patent Reference 1: Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-517242